484封装硬件做板差异点
芯片对比: PH1P100SBG484 VS PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准)
IO BANK 1, 3, 5, 7, 15, 20, 35
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 189 | 1 | IO_R1P_32,T0 | HR | 1 | T0 | - |
| 190 | 1 | IO_R1N_32,T0 | HR | 1 | T0 | - |
| 197 | 1 | IO_R5P_32,T0 | HR | 5 | T0 | - |
| 198 | 1 | IO_R5N_32,T0 | HR | 5 | T0 | - |
| 201 | 1 | IO_R7P_32,T1 | HR | 7 | T1 | - |
| 202 | 1 | IO_R7N_32,T1 | HR | 7 | T1 | - |
| 238 | 1 | VCCIO_33 | - | 35 | - | PH1P100器件VCCIO范围要求和XC7A100一致（1.14V-3.465V） |
| 243 | 1 | VCCIO_33 | - | 35 | - | - |
| 245 | 1 | IO_R1P_33,T0 | HR | 1 | T0_AD4P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 |
| 246 | 1 | IO_R1N_33,T0 | HR | 1 | T0_AD4N | - |
| 249 | 1 | IO_R3P_33,T0_DQS_P | HR | 3 | T0_DQS_AD5P | - |
| 250 | 1 | IO_R3N_33,T0_DQS_N | HR | 3 | T0_DQS_AD5N | - |
| 253 | 1 | IO_R5P_33,T0 | HR | 5 | T0_AD13P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 |
| 254 | 1 | IO_R5N_33,T0 | HR | 5 | T0_AD13N | - |
| 257 | 1 | IO_R7P_33,T1 | HR | 7 | T1_AD6P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 |
| 258 | 1 | IO_R7N_33,T1 | HR | 7 | T1_AD6N | - |
| 273 | 1 | IO_R15P_33,T2_DQS_P | HR | 15 | T2_DQS | - |
| 274 | 1 | IO_R15N_33,T2_DQS_N | HR | 15 | T2_DQS | - |
| 283 | 1 | IO_R20P_33,T3 | HR | 20 | T3 | - |
| 284 | 1 | IO_R20N_33,T3 | HR | 20 | T3 | - |
| 383 | 1 | GND | - | - | - | - |
| 418 | 1 | GND | - | - | - | - |
IO BANK 2, 3, 4, 8, 9, 16, 22, 34, 35
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 185 | 2 | VCCIO_32 | - | 34 | - | - |
| 191 | 2 | IO_R2P_32,T0 | HR | 2 | T0 | - |
| 192 | 2 | IO_R2N_32,T0 | HR | 2 | T0 | - |
| 194 | 2 | IO_R3N_32,T0_DQS_N | HR | 3 | T0_DQS | - |
| 195 | 2 | IO_R4P_32,T0 | HR | 4 | T0 | - |
| 196 | 2 | IO_R4N_32,T0 | HR | 4 | T0 | - |
| 204 | 2 | IO_R8N_32,T1 | HR | 8 | T1 | - |
| 239 | 2 | VCCIO_33 | - | 35 | - | - |
| 247 | 2 | IO_R2P_33,T0 | HR | 2 | T0_AD12P | - |
| 248 | 2 | IO_R2N_33,T0 | HR | 2 | T0_AD12N | - |
| 251 | 2 | IO_R4P_33,T0 | HR | 4 | T0 | - |
| 252 | 2 | IO_R4N_33,T0 | HR | 4 | T0 | - |
| 259 | 2 | IO_R8P_33,T1 | HR | 8 | T1_AD14P | - |
| 260 | 2 | IO_R8N_33,T1 | HR | 8 | T1_AD14N | - |
| 261 | 2 | IO_R9P_33,T1_DQS_P | HR | 9 | T1_DQS_AD7P | - |
| 262 | 2 | IO_R9N_33,T1_DQS_N | HR | 9 | T1_DQS_AD7N | - |
| 276 | 2 | IO_R16N_33,T2 | HR | 16 | T2 | - |
| 287 | 2 | IO_R22P_33,T3 | HR | 22 | T3 | - |
| 288 | 2 | IO_R22N_33,T3 | HR | 22 | T3 | - |
| 342 | 2 | GND | - | - | - | - |
| 349 | 2 | GND | - | - | - | - |
| 396 | 2 | GND | - | - | - | - |
IO BANK 0, 3, 6, 8, 9, 11, 14, 16, 19, 34, 35
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 187 | 3 | VCCIO_32 | - | 34 | - | - |
| 188 | 3 | IO_R0_32 | HR | 0 | - | - |
| 193 | 3 | IO_R3P_32,T0_DQS_P | HR | 3 | T0_DQS | - |
| 199 | 3 | IO_R6P_32,T0 | HR | 6 | T0 | - |
| 200 | 3 | IO_R6N_32,T0_VREF,T0 | HR | 6 | T0_VREF | - |
| 203 | 3 | IO_R8P_32,T1 | HR | 8 | T1 | - |
| 205 | 3 | IO_R9P_32,T1_DQS_P | HR | 9 | T1_DQS | - |
| 206 | 3 | IO_R9N_32,T1_DQS_N | HR | 9 | T1_DQS | - |
| 241 | 3 | VCCIO_33 | - | 35 | - | - |
| 255 | 3 | IO_R6P_33,T0 | HR | 6 | T0 | - |
| 256 | 3 | IO_R6N_33,T0_VREF,T0 | HR | 6 | T0_VREF | - |
| 265 | 3 | IO_R11P_33,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 266 | 3 | IO_R11N_33,GCLKIOC3,T1 | HR | 11 | T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 271 | 3 | IO_R14P_33,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 272 | 3 | IO_R14N_33,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 275 | 3 | IO_R16P_33,T2 | HR | 16 | T2 | - |
| 282 | 3 | IO_R19N_33,T3_VREF,T3 | HR | 19 | T3_VREF | - |
| 344 | 3 | GND | - | - | - | - |
| 355 | 3 | GND | - | - | - | - |
| 359 | 3 | GND | - | - | - | - |
| 363 | 3 | GND | - | - | - | - |
| 407 | 3 | GND | - | - | - | - |
IO BANK 0, 4, 11, 12, 13, 18, 19, 21, 34, 35, MGTAVTT
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 183 | 4 | VCCIO_32 | - | 34 | - | - |
| 209 | 4 | IO_R11P_32,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 210 | 4 | IO_R11N_32,GCLKIOC3,T1 | HR | 11 | T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 211 | 4 | IO_R12P_32,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 212 | 4 | IO_R12N_32,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 213 | 4 | IO_R13P_32,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 214 | 4 | IO_R13N_32,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 242 | 4 | VCCIO_33 | - | 35 | - | - |
| 244 | 4 | IO_R0_33 | HR | 0 | - | - |
| 267 | 4 | IO_R12P_33,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 268 | 4 | IO_R12N_33,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 269 | 4 | IO_R13P_33,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 270 | 4 | IO_R13N_33,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 280 | 4 | IO_R18N_33,T2 | HR | 18 | T2 | - |
| 281 | 4 | IO_R19P_33,T3 | HR | 19 | T3 | - |
| 286 | 4 | IO_R21N_33,T3_DQS_N | HR | 21 | T3_DQS | - |
| 298 | 4 | PHYVCCT_94 | - | MGTAVTT | - | - |
| 312 | 4 | TX0P_94 | - | 0 | - | - |
| 313 | 4 | TX0N_94 | - | 0 | - | - |
| 364 | 4 | GND | - | - | - | - |
| 368 | 4 | GND | - | - | - | - |
| 417 | 4 | GND | - | - | - | - |
IO BANK 1, 5, 10, 14, 15, 16, 18, 21, 23, 24, 34, MGTAVTT
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 184 | 5 | VCCIO_32 | - | 34 | - | - |
| 207 | 5 | IO_R10P_32,T1 | HR | 10 | T1 | - |
| 208 | 5 | IO_R10N_32,T1 | HR | 10 | T1 | - |
| 215 | 5 | IO_R14P_32,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 216 | 5 | IO_R14N_32,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 218 | 5 | IO_R15N_32,T2_DQS_N | HR | 15 | T2_DQS | - |
| 220 | 5 | IO_R16N_32,T2 | HR | 16 | T2 | - |
| 263 | 5 | IO_R10P_33,T1 | HR | 10 | T1_AD15P | - |
| 264 | 5 | IO_R10N_33,T1 | HR | 10 | T1_AD15N | - |
| 279 | 5 | IO_R18P_33,T2 | HR | 18 | T2 | - |
| 285 | 5 | IO_R21P_33,T3_DQS_P | HR | 21 | T3_DQS | - |
| 290 | 5 | IO_R23N_33,T3 | HR | 23 | T3 | - |
| 292 | 5 | IO_R24N_33,T3 | HR | 24 | T3 | - |
| 295 | 5 | PHYVCCT_94 | - | MGTAVTT | - | - |
| 314 | 5 | TX1P_94 | - | 1 | - | - |
| 315 | 5 | TX1N_94 | - | 1 | - | - |
| 345 | 5 | GND | - | - | - | - |
| 369 | 5 | GND | - | - | - | - |
| 374 | 5 | GND | - | - | - | - |
| 378 | 5 | GND | - | - | - | - |
| 394 | 5 | GND | - | - | - | - |
| 424 | 5 | GND | - | - | - | - |
IO BANK 0, 2, 6, 15, 16, 17, 18, 20, 23, 24, 25, 34, 35, MGTAVCC
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 186 | 6 | VCCIO_32 | - | 34 | - | - |
| 217 | 6 | IO_R15P_32,T2_DQS_P | HR | 15 | T2_DQS | - |
| 219 | 6 | IO_R16P_32,T2 | HR | 16 | T2 | - |
| 221 | 6 | IO_R17P_32,T2 | HR | 17 | T2 | - |
| 222 | 6 | IO_R17N_32,T2 | HR | 17 | T2 | - |
| 223 | 6 | IO_R18P_32,T2 | HR | 18 | T2 | - |
| 224 | 6 | IO_R18N_32,T2 | HR | 18 | T2 | - |
| 228 | 6 | IO_R20N_32,T3 | HR | 20 | T3 | - |
| 240 | 6 | VCCIO_33 | - | 35 | - | - |
| 277 | 6 | IO_R17P_33,T2 | HR | 17 | T2 | - |
| 278 | 6 | IO_R17N_33,T2 | HR | 17 | T2 | - |
| 289 | 6 | IO_R23P_33,T3 | HR | 23 | T3 | - |
| 291 | 6 | IO_R24P_33,T3 | HR | 24 | T3 | - |
| 293 | 6 | IO_R25_33 | HR | 25 | - | - |
| 300 | 6 | REFCLK0P_94 | - | 0 | - | - |
| 301 | 6 | REFCLK0N_94 | - | 0 | - | - |
| 316 | 6 | TX2P_94 | - | 2 | - | - |
| 317 | 6 | TX2N_94 | - | 2 | - | - |
| 360 | 6 | GND | - | - | - | - |
| 379 | 6 | GND | - | - | - | - |
| 403 | 6 | GND | - | - | - | - |
| 478 | 6 | NC | - | MGTAVCC | - | - |
IO BANK 3, 7, 19, 20, 23, 25, 34, MGTAVCC, MGTAVTT
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 182 | 7 | VCCIO_32 | - | 34 | - | PH1P100器件VCCIO范围要求和XC7A100一致（1.14V-3.465V） |
| 225 | 7 | IO_R19P_32,T3 | HR | 19 | T3 | - |
| 226 | 7 | IO_R19N_32,T3_VREF,T3 | HR | 19 | T3_VREF | - |
| 227 | 7 | IO_R20P_32,T3 | HR | 20 | T3 | - |
| 234 | 7 | IO_R23N_32,T3 | HR | 23 | T3 | - |
| 237 | 7 | IO_R25_32 | HR | 25 | - | - |
| 296 | 7 | PHYVCCT_94 | - | MGTAVTT | - | - |
| 318 | 7 | TX3P_94 | - | 3 | - | - |
| 319 | 7 | TX3N_94 | - | 3 | - | - |
| 323 | 7 | VCCINT | - | - | - | - |
| 326 | 7 | VCCINT | - | - | - | - |
| 328 | 7 | VCCINT | - | - | - | - |
| 331 | 7 | VCCINT | - | - | - | - |
| 346 | 7 | GND | - | - | - | - |
| 370 | 7 | GND | - | - | - | - |
| 380 | 7 | GND | - | - | - | - |
| 386 | 7 | GND | - | - | - | - |
| 395 | 7 | GND | - | - | - | - |
| 401 | 7 | GND | - | - | - | - |
| 408 | 7 | GND | - | - | - | - |
| 415 | 7 | GND | - | - | - | - |
| 480 | 7 | NC | - | MGTAVCC | - | - |
IO BANK 0, 8, 21, 22, 23, 216, MGTAVCC, MGTAVTT
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 230 | 8 | IO_R21N_32,T3_DQS_N | HR | 21 | T3_DQS | - |
| 231 | 8 | IO_R22P_32,T3 | HR | 22 | T3 | - |
| 232 | 8 | IO_R22N_32,T3 | HR | 22 | T3 | - |
| 233 | 8 | IO_R23P_32,T3 | HR | 23 | T3 | - |
| 299 | 8 | PHYVCCT_94 | - | MGTAVTT | - | - |
| 304 | 8 | RX0P_94 | - | 0 | - | - |
| 305 | 8 | RX0N_94 | - | 0 | - | - |
| 320 | 8 | RESREF_94 | - | 216 | - | - |
| 322 | 8 | VCCINT | - | - | - | - |
| 325 | 8 | VCCINT | - | - | - | - |
| 327 | 8 | VCCINT | - | - | - | - |
| 330 | 8 | VCCINT | - | - | - | - |
| 334 | 8 | VCCINT | - | - | - | - |
| 365 | 8 | GND | - | - | - | - |
| 381 | 8 | GND | - | - | - | - |
| 391 | 8 | GND | - | - | - | - |
| 398 | 8 | GND | - | - | - | - |
| 404 | 8 | GND | - | - | - | - |
| 412 | 8 | GND | - | - | - | - |
| 422 | 8 | GND | - | - | - | - |
| 473 | 8 | NC | - | 0 | - | XC7A100用来控制多个config IO BANK的电压配置；PH1P100不支持 |
| 479 | 8 | NC | - | MGTAVCC | - | - |
IO BANK 0, 2, 3, 8, 9, 21, 24, MGTAVCC, MGTAVTT
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 13 | 9 | M2_0 | - | 2 | - | - |
| 229 | 9 | IO_R21P_32,T3_DQS_P | HR | 21 | T3_DQS | - |
| 235 | 9 | IO_R24P_32,T3 | HR | 24 | T3 | - |
| 236 | 9 | IO_R24N_32,T3 | HR | 24 | T3 | - |
| 297 | 9 | PHYVCCT_94 | - | MGTAVTT | - | - |
| 310 | 9 | RX3P_94 | - | 3 | - | - |
| 311 | 9 | RX3N_94 | - | 3 | - | - |
| 324 | 9 | VCCINT | - | - | - | - |
| 332 | 9 | VCCINT | - | - | - | - |
| 347 | 9 | GND | - | - | - | - |
| 352 | 9 | GND | - | - | - | - |
| 371 | 9 | GND | - | - | - | - |
| 382 | 9 | GND | - | - | - | - |
| 387 | 9 | GND | - | - | - | - |
| 409 | 9 | GND | - | - | - | - |
| 426 | 9 | GND | - | - | - | - |
| 447 | 9 | IO_L8P_11,T1 | HR | 8 | T1 | - |
| 468 | 9 | NC | - | 0 | - | - |
| 470 | 9 | NC | - | 0 | - | - |
| 472 | 9 | NC | - | 0 | - | - |
| 474 | 9 | NC | - | 0 | - | XC7A100的sensor；PH1P100不支持 |
| 481 | 9 | NC | - | MGTAVCC | - | - |
IO BANK 0, 1, 2, 8, 9, 10, 13, MGTAVCC
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 12 | 10 | M1_0 | - | 1 | - | - |
| 302 | 10 | REFCLK1P_94 | - | 1 | - | - |
| 303 | 10 | REFCLK1N_94 | - | 1 | - | - |
| 308 | 10 | RX2P_94 | - | 2 | - | - |
| 309 | 10 | RX2N_94 | - | 2 | - | - |
| 321 | 10 | VCCINT | - | - | - | PH1P100器件典型值为0.95V(0.92-0.98V)，XC7A100器件典型值为1.0V(0.95~1.05V) |
| 329 | 10 | VCCINT | - | - | - | - |
| 333 | 10 | VCCINT | - | - | - | - |
| 356 | 10 | GND | - | - | - | - |
| 375 | 10 | GND | - | - | - | - |
| 388 | 10 | GND | - | - | - | - |
| 410 | 10 | GND | - | - | - | - |
| 431 | 10 | VCCIO_11 | - | 13 | - | - |
| 448 | 10 | IO_L8N_11,T1 | HR | 8 | T1 | - |
| 449 | 10 | IO_L9P_11,T1_DQS_P | HR | 9 | T1_DQS | - |
| 451 | 10 | IO_L10P_11,T1 | HR | 10 | T1 | - |
| 452 | 10 | IO_L10N_11,T1 | HR | 10 | T1 | - |
| 467 | 10 | NC | - | 0 | - | XC7A100支持ADC；PH1P100不支持 |
| 469 | 10 | NC | - | 0 | - | - |
| 471 | 10 | NC | - | 0 | - | - |
| 475 | 10 | NC | - | 0 | - | - |
| 477 | 10 | NC | - | MGTAVCC | - | XC7A100的MGTAVTT为1.2V，MGTAVCC为1.0V |
IO BANK 0, 1, 7, 9, 11, 12, MGTAVTT, VCCAUX, VCCBRAM
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 10 | 11 | DONE_0 | - | 0 | - | PH1P100需要上拉，推荐使用4.7KΩ，XC7A100推荐使用330Ω |
| 11 | 11 | M0_0 | - | 0 | - | - |
| 294 | 11 | PHYVCCT_94 | - | MGTAVTT | - | PH1P100的HXT电源为1.2V,XC7A100T的MGTAVTT为1.2V，MGTAVCC为1.0V |
| 306 | 11 | RX1P_94 | - | 1 | - | - |
| 307 | 11 | RX1N_94 | - | 1 | - | - |
| 336 | 11 | VCCAUX | - | VCCAUX | - | - |
| 340 | 11 | GND | - | - | - | - |
| 366 | 11 | GND | - | - | - | - |
| 372 | 11 | GND | - | - | - | - |
| 384 | 11 | GND | - | - | - | - |
| 392 | 11 | GND | - | - | - | - |
| 399 | 11 | GND | - | - | - | - |
| 405 | 11 | GND | - | - | - | - |
| 413 | 11 | GND | - | - | - | - |
| 419 | 11 | GND | - | - | - | - |
| 445 | 11 | IO_L7P_11,T1 | HR | 7 | T1 | - |
| 450 | 11 | IO_L9N_11,T1_DQS_N | HR | 9 | T1_DQS | - |
| 453 | 11 | IO_L11P_11,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 455 | 11 | IO_L12P_11,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 482 | 11 | NC | - | VCCBRAM | - | XC7A100的BRAM供电电源VCCBRAM,为0.95V；PH1P100不支持 |
| 483 | 11 | NC | - | VCCBRAM | - | - |
| 484 | 11 | NC | - | VCCBRAM | - | - |
IO BANK 0, 7, 11, 12, VCCAUX
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 1 | 12 | VCCIO_0 | - | 0 | - | PH1P100供电范围1.71V~3.465V |
| 2 | 12 | VCCIO_0 | - | 0 | - | - |
| 3 | 12 | IO_C0_0,CCLK_0 | HD | 0 | - | PH1P100可在用户阶段作为普通IO使用，XC7A100为专用管脚 |
| 4 | 12 | TCK_0 | - | 0 | - | PH1P100需要外接4.7KΩ上拉电阻 |
| XC7A100器件TMS和TCK需要4.7K上拉 | ||||||
| 8 | 12 | INITN_0 | - | 0 | - | - |
| 9 | 12 | PROGRAMN_0 | - | 0 | - | - |
| 335 | 12 | VCCAUX | - | VCCAUX | - | PH1P100器件的VCCAUX分为VCCAUX和VCCAUX_IO，应用时必须都供电，典型值为1.8V(1.71~1.89V) |
| XC7A100器件的VCCAUX典型值为1.8V(1.71~1.89) | ||||||
| 337 | 12 | VCCAUX_IO | - | VCCAUX | - | - |
| 338 | 12 | VCCAUX_IO | - | VCCAUX | - | - |
| 339 | 12 | VCCAUX_IO | - | VCCAUX | - | - |
| 341 | 12 | GND | - | - | - | - |
| 348 | 12 | GND | - | - | - | - |
| 353 | 12 | GND | - | - | - | - |
| 357 | 12 | GND | - | - | - | - |
| 361 | 12 | GND | - | - | - | - |
| 376 | 12 | GND | - | - | - | - |
| 389 | 12 | GND | - | - | - | - |
| 425 | 12 | GND | - | - | - | - |
| 446 | 12 | IO_L7N_11,T1 | HR | 7 | T1 | - |
| 454 | 12 | IO_L11N_11,GCLKIOC3,T1 | HR | 11 | T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 456 | 12 | IO_L12N_11,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 476 | 12 | NC | - | 0 | - | XC7A100的电池电源VCCBATT_0，范围为1.0-1.89V；PH1P100不支持 |
IO BANK 0, 1, 3, 4, 5, 8, 10, 13, 15, 19, 20, 23
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 5 | 13 | TMS_0 | - | 0 | - | - |
| 6 | 13 | TDO_0 | - | 0 | - | - |
| 7 | 13 | TDI_0 | - | 0 | - | - |
| 65 | 13 | IO_L23P_12,D19,T3 | HR | 23 | T3_A03_D19 | - |
| 72 | 13 | VCCIO_13 | - | 15 | - | - |
| 77 | 13 | IO_L1P_13,T0 | HR | 1 | T0_AD0P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 |
| 78 | 13 | IO_L1N_13,T0 | HR | 1 | T0_AD0N | - |
| 113 | 13 | IO_L19P_13,T3 | HR | 19 | T3_A22 | - |
| 115 | 13 | IO_L20P_13,T3 | HR | 20 | T3_A20 | - |
| 116 | 13 | IO_L20N_13,T3 | HR | 20 | T3_A19 | - |
| 133 | 13 | IO_L1P_14,T0 | HR | 1 | T0 | - |
| 139 | 13 | IO_L4P_14,T0 | HR | 4 | T0 | - |
| 147 | 13 | IO_L8P_14,T1 | HR | 8 | T1 | - |
| 148 | 13 | IO_L8N_14,T1 | HR | 8 | T1 | - |
| 151 | 13 | IO_L10P_14,T1 | HR | 10 | T1 | - |
| 362 | 13 | GND | - | - | - | - |
| 406 | 13 | GND | - | - | - | - |
| 430 | 13 | VCCIO_11 | - | 13 | - | - |
| 437 | 13 | IO_L3P_11,T0_DQS_P | HR | 3 | T0_DQS | - |
| 438 | 13 | IO_L3N_11,T0_DQS_N | HR | 3 | T0_DQS | - |
| 441 | 13 | IO_L5P_11,T0 | HR | 5 | T0 | - |
| 457 | 13 | IO_L13P_11,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
IO BANK 1, 3, 4, 5, 6, 10, 13, 14, 15, 16, 19, 22, 23
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 14 | 14 | VCCIO_12 | - | 14 | - | PH1P100器件VCCIO范围要求和XC7A50一致（1.14V-3.465V） |
| 57 | 14 | IO_L19P_12,D26,T3 | HR | 19 | T3_A10_D26 | - |
| 58 | 14 | IO_L19N_12,D25,T3_VREF,T3 | HR | 19 | T3_A09_D25_VREF | - |
| 66 | 14 | IO_L23N_12,D18,T3 | HR | 23 | T3_A02_D18 | - |
| 81 | 14 | IO_L3P_13,T0_DQS_P | HR | 3 | T0_DQS_AD1P | - |
| 82 | 14 | IO_L3N_13,T0_DQS_N | HR | 3 | T0_DQS_AD1N | - |
| 114 | 14 | IO_L19N_13,T3_VREF,T3 | HR | 19 | T3_A21_VREF | - |
| 119 | 14 | IO_L22P_13,T3 | HR | 22 | T3_A17 | - |
| 127 | 14 | VCCIO_14 | - | 16 | - | - |
| 134 | 14 | IO_L1N_14,T0 | HR | 1 | T0 | - |
| 137 | 14 | IO_L3P_14,T0_DQS_P | HR | 3 | T0_DQS | - |
| 140 | 14 | IO_L4N_14,T0 | HR | 4 | T0 | - |
| 143 | 14 | IO_L6P_14,T0 | HR | 6 | T0 | - |
| 152 | 14 | IO_L10N_14,T1 | HR | 10 | T1 | - |
| 377 | 14 | GND | - | - | - | - |
| 416 | 14 | GND | - | - | - | - |
| 428 | 14 | VCCIO_11 | - | 13 | - | - |
| 442 | 14 | IO_L5N_11,T0 | HR | 5 | T0 | - |
| 443 | 14 | IO_L6P_11,T0 | HR | 6 | T0 | - |
| 444 | 14 | IO_L6N_11,T0_VREF,T0 | HR | 6 | T0_VREF | - |
| 458 | 14 | IO_L13N_11,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 461 | 14 | IO_L15P_11,T2_DQS_P | HR | 15 | T2_DQS | - |
IO BANK 0, 2, 3, 4, 5, 6, 7, 9, 14, 15, 16, 22, 24, 25
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 16 | 15 | VCCIO_12 | - | 14 | - | - |
| 63 | 15 | IO_L22P_12,D21,T3 | HR | 22 | T3_A05_D21 | - |
| 69 | 15 | IO_L25_12 | HR | 25 | - | - |
| 79 | 15 | IO_L2P_13,T0 | HR | 2 | T0_AD8P | - |
| 85 | 15 | IO_L5P_13,T0 | HR | 5 | T0_AD9P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 |
| 86 | 15 | IO_L5N_13,T0 | HR | 5 | T0_AD9N | - |
| 120 | 15 | IO_L22N_13,T3 | HR | 22 | T3_A16 | - |
| 123 | 15 | IO_L24P_13,T3 | HR | 24 | T3_RS1 | RS0/RS1为revision select output；PH1P100不支持 |
| 130 | 15 | VCCIO_14 | - | 16 | - | - |
| 132 | 15 | IO_L0_14 | HR | 0 | - | - |
| 138 | 15 | IO_L3N_14,T0_DQS_N | HR | 3 | T0_DQS | - |
| 144 | 15 | IO_L6N_14,T0_VREF,T0 | HR | 6 | T0_VREF | - |
| 145 | 15 | IO_L7P_14,T1 | HR | 7 | T1 | - |
| 149 | 15 | IO_L9P_14,T1_DQS_P | HR | 9 | T1_DQS | - |
| 393 | 15 | GND | - | - | - | - |
| 423 | 15 | GND | - | - | - | - |
| 439 | 15 | IO_L4P_11,T0 | HR | 4 | T0 | - |
| 440 | 15 | IO_L4N_11,T0 | HR | 4 | T0 | - |
| 459 | 15 | IO_L14P_11,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 460 | 15 | IO_L14N_11,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 462 | 15 | IO_L15N_11,T2_DQS_N | HR | 15 | T2_DQS | - |
| 463 | 15 | IO_L16P_11,T2 | HR | 16 | T2 | - |
IO BANK 0, 1, 2, 5, 7, 9, 13, 15, 16, 17, 22, 23, 24
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 64 | 16 | IO_L22N_12,D20,T3 | HR | 22 | T3_A04_D20 | - |
| 67 | 16 | IO_L24P_12,D17,T3 | HR | 24 | T3_A01_D17 | - |
| 71 | 16 | VCCIO_13 | - | 15 | - | - |
| 76 | 16 | IO_L0_13 | HR | 0 | - | - |
| 80 | 16 | IO_L2N_13,T0 | HR | 2 | T0_AD8N | - |
| 121 | 16 | IO_L23P_13,T3 | HR | 23 | T3_FOE_B | XC7A100支持BPI,FOE是flash输出使能；PH1P100不支持 |
| 122 | 16 | IO_L23N_13,T3 | HR | 23 | T3_FWE_B | XC7A100支持BPI,FOE是flash片选；PH1P100不支持 |
| 124 | 16 | IO_L24N_13,T3 | HR | 24 | T3_RS0 | - |
| 135 | 16 | IO_L2P_14,T0 | HR | 2 | T0 | - |
| 141 | 16 | IO_L5P_14,T0 | HR | 5 | T0 | - |
| 142 | 16 | IO_L5N_14,T0 | HR | 5 | T0 | - |
| 146 | 16 | IO_L7N_14,T1 | HR | 7 | T1 | - |
| 150 | 16 | IO_L9N_14,T1_DQS_N | HR | 9 | T1_DQS | - |
| 358 | 16 | GND | - | - | - | - |
| 402 | 16 | GND | - | - | - | - |
| 429 | 16 | VCCIO_11 | - | 13 | - | - |
| 433 | 16 | IO_L1P_11,T0 | HR | 1 | T0 | - |
| 434 | 16 | IO_L1N_11,T0 | HR | 1 | T0 | - |
| 435 | 16 | IO_L2P_11,T0 | HR | 2 | T0 | - |
| 464 | 16 | IO_L16N_11,T2 | HR | 16 | T2 | - |
| 465 | 16 | IO_L17P_11,T2 | HR | 17 | T2 | - |
| 466 | 16 | IO_L17N_11,T2 | HR | 17 | T2 | - |
IO BANK 0, 2, 4, 6, 11, 12, 13, 15, 16, 17, 18, 21, 24, 25
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 51 | 17 | IO_L16P_12,CSN,T2 | HR | 16 | T2_CSI_B | - |
| 52 | 17 | IO_L16N_12,D31,T2 | HR | 16 | T2_A15_D31 | XC7A100支持BPI,A00-A28是地址输出；PH1P100不支持 |
| 55 | 17 | IO_L18P_12,D28,T2 | HR | 18 | T2_A12_D28 | - |
| 61 | 17 | IO_L21P_12,T3_DQS_P | HR | 21 | T3_DQS | - |
| 62 | 17 | IO_L21N_12,D22,T3_DQS_N | HR | 21 | T3_DQS_A06_D22 | XC7A100支持BPI,A00-A28是地址输出；PH1P100不支持 |
| 68 | 17 | IO_L24N_12,D16,T3 | HR | 24 | T3_A00_D16 | - |
| 74 | 17 | VCCIO_13 | - | 15 | - | - |
| 83 | 17 | IO_L4P_13,T0 | HR | 4 | T0 | - |
| 87 | 17 | IO_L6P_13,T0 | HR | 6 | T0 | - |
| 117 | 17 | IO_L21P_13,T3_DQS_P | HR | 21 | T3_DQS | - |
| 118 | 17 | IO_L21N_13,T3_DQS_N | HR | 21 | T3_DQS_A18 | XC7A100支持BPI,A00-A28是地址输出；PH1P100不支持 |
| 125 | 17 | IO_L25_13 | HR | 25 | - | - |
| 126 | 17 | VCCIO_14 | - | 16 | - | PH1P100器件VCCIO范围要求和XC7A100一致（1.14V-3.465V） |
| 136 | 17 | IO_L2N_14,T0 | HR | 2 | T0 | - |
| 153 | 17 | IO_L11P_14,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 155 | 17 | IO_L12P_14,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 156 | 17 | IO_L12N_14,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 373 | 17 | GND | - | - | - | - |
| 414 | 17 | GND | - | - | - | - |
| 427 | 17 | VCCIO_11 | - | 13 | - | PH1P100器件VCCIO范围要求和XC7A100一致（1.14V-3.465V） |
| 432 | 17 | IO_L0_11 | HR | 0 | - | - |
| 436 | 17 | IO_L2N_11,T0 | HR | 2 | T0 | - |
IO BANK 4, 6, 11, 13, 14, 15, 16, 17, 18, 20
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 15 | 18 | VCCIO_12 | - | 14 | - | - |
| 45 | 18 | IO_L13P_12,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 47 | 18 | IO_L14P_12,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 53 | 18 | IO_L17P_12,D30,T2 | HR | 17 | T2_A14_D30 | - |
| 54 | 18 | IO_L17N_12,D29,T2 | HR | 17 | T2_A13_D29 | - |
| 56 | 18 | IO_L18N_12,D27,T2 | HR | 18 | T2_A11_D27 | - |
| 59 | 18 | IO_L20P_12,D24,T3 | HR | 20 | T3_A08_D24 | - |
| 60 | 18 | IO_L20N_12,D23,T3 | HR | 20 | T3_A07_D23 | - |
| 84 | 18 | IO_L4N_13,T0 | HR | 4 | T0 | - |
| 88 | 18 | IO_L6N_13,T0_VREF,T0 | HR | 6 | T0_VREF | - |
| 101 | 18 | IO_L13P_13,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 107 | 18 | IO_L16P_13,T2 | HR | 16 | T2_A28 | XC7A100支持BPI,A00-A28是地址输出；PH1P100不支持 |
| 108 | 18 | IO_L16N_13,T2 | HR | 16 | T2_A27 | - |
| 109 | 18 | IO_L17P_13,T2 | HR | 17 | T2_A26 | - |
| 129 | 18 | VCCIO_14 | - | 16 | - | - |
| 154 | 18 | IO_L11N_14,GCLKIOC3,T1 | HR | 11 | T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 157 | 18 | IO_L13P_14,GCLKIOT1,T2 | HR | 13 | T2_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 161 | 18 | IO_L15P_14,T2_DQS_P | HR | 15 | T2_DQS | - |
| 162 | 18 | IO_L15N_14,T2_DQS_N | HR | 15 | T2_DQS | - |
| 165 | 18 | IO_L17P_14,T2 | HR | 17 | T2 | - |
| 390 | 18 | GND | - | - | - | - |
| 421 | 18 | GND | - | - | - | - |
IO BANK 5, 6, 12, 13, 14, 15, 17, 18, 19
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 18 | 19 | VCCIO_12 | - | 14 | - | - |
| 29 | 19 | IO_L5P_12,D6,T0 | HR | 5 | T0_D06 | - |
| 30 | 19 | IO_L5N_12,D7,T0 | HR | 5 | T0_D07 | - |
| 31 | 19 | IO_L6P_12,SPICSN,BUSY,T0 | HR | 6 | T0_FCS_B | XC7A100器件为BPI和SPI模式的FLASH片选信号，低有效 |
| PH1P100器件为MSPI FLASH片选信号，BUSY信号为回读数据指示信号，低有效 | ||||||
| 43 | 19 | IO_L12P_12,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 46 | 19 | IO_L13N_12,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 48 | 19 | IO_L14N_12,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 49 | 19 | IO_L15P_12,RDWRN,T2_DQS_P | HR | 15 | T2_DQS_RDWR_B | - |
| 70 | 19 | VCCIO_13 | - | 15 | - | - |
| 99 | 19 | IO_L12P_13,GCLKIOT2,T1 | HR | 12 | T1_MRCC | PH1P100是全局时钟输入引脚，XC7A100是多区域时钟输入引脚。单端和差分均可从P端口输入 |
| 100 | 19 | IO_L12N_13,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 102 | 19 | IO_L13N_13,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 103 | 19 | IO_L14P_13,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 110 | 19 | IO_L17N_13,T2 | HR | 17 | T2_A25 | - |
| 158 | 19 | IO_L13N_14,GCLKIOC1,T2 | HR | 13 | T2_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 159 | 19 | IO_L14P_14,GCLKIOT0,T2 | HR | 14 | T2_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 160 | 19 | IO_L14N_14,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 166 | 19 | IO_L17N_14,T2 | HR | 17 | T2 | - |
| 167 | 19 | IO_L18P_14,T2 | HR | 18 | T2 | - |
| 351 | 19 | GND | - | - | - | - |
| 354 | 19 | GND | - | - | - | - |
| 400 | 19 | GND | - | - | - | - |
IO BANK 0, 6, 8, 11, 12, 14, 15, 16, 18, 19, 20
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 19 | 20 | VCCIO_12 | - | 14 | - | - |
| 20 | 20 | IO_L0_12 | HR | 0 | - | - |
| 32 | 20 | IO_L6N_12,D8,T0_VREF,T0 | HR | 6 | T0_D08_VREF | - |
| 35 | 20 | IO_L8P_12,D11,T1 | HR | 8 | T1_D11 | - |
| 41 | 20 | IO_L11P_12,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 42 | 20 | IO_L11N_12,GCLKIOC3,T1 | HR | 11 | T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 44 | 20 | IO_L12N_12,GCLKIOC2,T1 | HR | 12 | T1_MRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 50 | 20 | IO_L15N_12,CSON,DOUT,T2_DQS_N | HR | 15 | T2_DQS_DOUT_CSO_B | - |
| 73 | 20 | VCCIO_13 | - | 15 | - | - |
| 91 | 20 | IO_L8P_13,T1 | HR | 8 | T1_AD10P | - |
| 92 | 20 | IO_L8N_13,T1 | HR | 8 | T1_AD10N | - |
| 97 | 20 | IO_L11P_13,GCLKIOT3,T1 | HR | 11 | T1_SRCC | PH1P100是全局时钟输入引脚，XC7A100是单区域时钟输入引脚。单端和差分均可从P端口输入 |
| 104 | 20 | IO_L14N_13,GCLKIOC0,T2 | HR | 14 | T2_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 111 | 20 | IO_L18P_13,T2 | HR | 18 | T2_A24 | - |
| 112 | 20 | IO_L18N_13,T2 | HR | 18 | T2_A23 | - |
| 163 | 20 | IO_L16P_14,T2 | HR | 16 | T2 | - |
| 164 | 20 | IO_L16N_14,T2 | HR | 16 | T2 | - |
| 168 | 20 | IO_L18N_14,T2 | HR | 18 | T2 | - |
| 169 | 20 | IO_L19P_14,T3 | HR | 19 | T3 | - |
| 170 | 20 | IO_L19N_14,T3_VREF,T3 | HR | 19 | T3_VREF | - |
| 367 | 20 | GND | - | - | - | - |
| 411 | 20 | GND | - | - | - | - |
IO BANK 2, 4, 7, 8, 9, 10, 11, 15, 16, 21, 23, 24, 25
| PH1P100SBG484 | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | |||||
|---|---|---|---|---|---|---|
| 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 |
| 23 | 21 | IO_L2P_12,D2,WPN,T0 | HR | 2 | T0_D02 | - |
| 24 | 21 | IO_L2N_12,D3,HOLDN,T0 | HR | 2 | T0_D03 | - |
| 27 | 21 | IO_L4P_12,D4,T0 | HR | 4 | T0_D04 | - |
| 28 | 21 | IO_L4N_12,D5,T0 | HR | 4 | T0_D05 | - |
| 33 | 21 | IO_L7P_12,D9,T1 | HR | 7 | T1_D09 | - |
| 36 | 21 | IO_L8N_12,D12,T1 | HR | 8 | T1_D12 | - |
| 37 | 21 | IO_L9P_12,T1_DQS_P | HR | 9 | T1_DQS | - |
| 39 | 21 | IO_L10P_12,D14,T1 | HR | 10 | T1_D14 | - |
| 75 | 21 | VCCIO_13 | - | 15 | - | - |
| 93 | 21 | IO_L9P_13,T1_DQS_P | HR | 9 | T1_DQS_AD3P | - |
| 95 | 21 | IO_L10P_13,T1 | HR | 10 | T1_AD11P | - |
| 96 | 21 | IO_L10N_13,T1 | HR | 10 | T1_AD11N | - |
| 98 | 21 | IO_L11N_13,GCLKIOC3,T1 | HR | 11 | _T1_SRCC | PH1P100和XC7A100的差分时钟N端输入，不可输入单端时钟 |
| 128 | 21 | VCCIO_14 | - | 16 | - | - |
| 173 | 21 | IO_L21P_14,T3_DQS_P | HR | 21 | T3_DQS | - |
| 174 | 21 | IO_L21N_14,T3_DQS_N | HR | 21 | T3_DQS | - |
| 177 | 21 | IO_L23P_14,T3 | HR | 23 | T3 | - |
| 178 | 21 | IO_L23N_14,T3 | HR | 23 | T3 | - |
| 179 | 21 | IO_L24P_14,T3 | HR | 24 | T3 | - |
| 181 | 21 | IO_L25_14 | HR | 25 | - | - |
| 385 | 21 | GND | - | - | - | - |
| 420 | 21 | GND | - | - | - | - |
IO BANK 1, 3, 7, 9, 10, 14, 15, 16, 20, 22, 24
| PH1P100SBG484 | | | PH1P100SBG484 与 对标器件 引脚差异对照表V1.0 (仅列出相关引脚键差异对比，仅供设计参考。本文档不随数据手册同步更新，具体设计请以最新版本数据手册引脚信息章节描述为准) | | | | | 引脚编号 | IO BANK | 引脚说明 | 引脚编号 | IO BANK | 引脚说明 | 差异备注 | |———-|———|———-|———-|———|———-|———-| | 17 | 22 | VCCIO_12 | - | 14 | - | - | | 21 | 22 | IO_L1P_12,D0,MOSI,T0 | HR | 1 | T0_D00_MOSI | - | | 22 | 22 | IO_L1N_12,D1,MISO,DIN,T0 | HR | 1 | T0_D01_DIN | - | | 25 | 22 | IO_L3P_12,HSWAPEN,T0_DQS_P | HR | 3 | T0_DQS_PUDC_B | PH1P100为控制I/O管脚在配置过程中的状态。 HSWAPEN=0，用户I/O管脚在配置过程中为弱上拉状态 HSWAPEN=1，用户I/O管脚在配置过程中为高阻态。 XC7A100的PUDC_B名称不同，功能一致。 | | 26 | 22 | IO_L3N_12,USRCLK,T0_DQS_N | HR | 3 | T0_DQS_EMCCLK | PH1P100当作测试引脚使用，XC7A100当作外部主动配置的时钟源 | | 34 | 22 | IO_L7N_12,D10,T1 | HR | 7 | T1_D10 | - | | 38 | 22 | IO_L9N_12,D13,T1_DQS_N | HR | 9 | T1_DQS_D13 | - | | 40 | 22 | IO_L10N_12,D15,T1 | HR | 10 | T1_D15 | - | | 89 | 22 | IO_L7P_13,T1 | HR | 7 | T1_AD2P | XC7A100支持ADC,ADXP/ADXN是模拟通道输入；PH1P100不支持 | | 90 | 22 | IO_L7N_13,T1 | HR | 7 | T1_AD2N | - | | 94 | 22 | IO_L9N_13,T1_DQS_N | HR | 9 | T1_DQS_AD3N | - | | 105 | 22 | IO_L15P_13,T2_DQS_P | HR | 15 | T2_DQS | - | | 106 | 22 | IO_L15N_13,T2_DQS_N | HR | 15 | T2_DQS_ADV_B | XC7A100支持BPI,ADV为flash地址输出；PH1P100不支持 | | 131 | 22 | VCCIO_14 | - | 16 | - | - | | 171 | 22 | IO_L20P_14,T3 | HR | 20 | T3 | - | | 172 | 22 | IO_L20N_14,T3 | HR | 20 | T3 | - | | 175 | 22 | IO_L22P_14,T3 | HR | 22 | T3 | - | | 176 | 22 | IO_L22N_14,T3 | HR | 22 | T3 | - | | 180 | 22 | IO_L24N_14,T3 | HR | 24 | T3 | - | | 343 | 22 | GND | - | - | - | - | | 350 | 22 | GND | - | - | - | - | | 397 | 22 | GND | - | - | - | - |